
28 nm Device Portfolio
Arria V ST SoC Features
Maximum Resource Count for Arria V ST SoCs (1.1 V) 1
5ASTD3
5ASTD5
PLLs (FPGA)
PLLs (HPS)
ALMs
LEs (K)
Registers
M10K memory blocks
M10K memory (Kb)
MLAB memory (Kb)
Variable-precision DSP blocks
18 x 18 multipliers
Processor cores (ARM Cortex-A9)
Global clock networks
2
2
Design security
I/O voltage levels supported (V)
132,075
350
528,300
1,729
17,288
2,014
809
1,618
Dual
10
3
16
3
1.2, 1.5, 1.8, 2.5, 3.0, 3.3
174,340
462
697,360
2,282
22,820
2,658
1,068
2,186
Dual
14
3
LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, Differential SSTL-15,
I/O standards supported
Differential SSTL-18, Differential SSTL-2, Differential HSTL-12, Differential HSTL-15,
Differential HSTL-18, SSTL-15 (I and II), SSTL-18 (I and II), SSTL-2 (I and II),
1.2 V HSTL (I and II), 1.5 V HSTL (I and II), 1.8 V HSTL (I and II)
Hard memory controllers (HPS)
LVDStransmitter(TX)
LVDS receiver (RX)
Embedded DPA circuitry
OCT
Programmable drive strength
Transceiver count
(10.3125 Gbps/6.5536 Gbps)
PCIe hard IP blocks (Gen2 x4)
GPIOs (FPGA)
GPIOs (HPS)
Hard memory controllers 3 (FPGA)
3
136
121
16/30
2
528
216
3
1
3
Series and differential
3
136
121
16/30
2
528
216
3
1
Memory devices supported
DDR3, DDR2, DDR, QDR II, QDR II+, RLDRAM II, LPDDR2 4 , SDR
1
2
3
4
All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.altera.com.
The PLL count includes general-purpose fractional PLLs and transceiver fractional PLLs.
With 16 and 32 bit ECC support.
These memory interfaces are not available as Altera IP.
16
Altera Product Catalog
?
2013
?
www.altera.com